Software-Hardware Co-design Page

Hardware / Software Co-design Team

Computing Systems Laboratory (CSLAB)

Welcome to the Hardware/Software Co-design Page of NTUA's Computing Systems Laboratory (CSLAB). Hardware/Software Co-design refers to design methodologies that divide the implementation of an algorithm into parts that can directly be mapped on hardware modules (Field Programmable Gate Arrays, FPGA) and parts that will be executed on a conventional microprocessor, proposing also an efficient communication scheme between the hardware modules and the microprocessor. This site offers an automated tool for the implementation of Embedded Systems for Syntactic Pattern Recognition applications.

Computing Systems Laboratory

The National Technical University of Athens (NTUA) is the leading and most prestigious Technical University in Greece. The Computing Systems Laboratory (CSLab) is one of the largest research laboratories in the Computer Science Division of the Department of Electrical and Computer Engineering, NTUA. The lab has large involvement and participation in research and technological development (RTD) projects with strong national and european research partnerships. Its large computing infrastructure comprises several SMP architectures and various PC linux clusters from off-the-shelf nodes with high performance interconnects (SCI, GbE, Myrinet).

CSLab activities span both research and academic/teaching areas, mainly focusing on the following research fields:

Parallel and Distributed Computing Systems
High Performance Computing and Networking Architectures
Operating Systems Support
High Level Hardware Design Automation
Embedded (Networking) Systems
Intelligent Computing Systems
High Performance Medical Applications

The Hardware/Software Co-design team is part of the High Level Hardware Design Automation group.The underlying model of the proposed architectures is that of Grammars (Context-free grammars and Attribute Grammars). The last ones can be used in a considerable number of applications of Artificial Intelligence and Syntactic Pattern Recognition. The proposed methodology is based on the mapping of the syntactic part of grammar on hardware (FPGA), while the semantic part on a conventional microprocessor.